Huawei reveals Kirin 2026 chip real test outcomes in updated Tau Law paper

Huawei Semiconductor Business Unit President He Tingbo presented an updated Tau Law paper that reveals the real test outcomes of the Kirin 2026 chip series. From heat dissipation to power consumption, here’s what the upcoming mobile SoCs can offer.

Tingbo released the updated Tau Law paper and shed light on the real-world test results of the Huawei Kirin 2026 chip. She found that the transistor density of the new chipsets has increased by 55%, while reducing NPU power consumption by 66%.

On the other hand, the GPU and CPU power consumption has dropped by 58% and 41%, respectively, compared to the Kirin 9030 Pro under the same performance conditions. Why so? Let’s find out.

According to the chief scientist, the main energy consumption does not come from the computing process inside the chip but from data transmission.

The updated Tau Law paper significantly focuses on heat dissipation and power consumption issues that became a hot topic with the introduction of LogicFolding.

Going with the traditional view, vertically stacking active transistors can raise the power density and heat generation per unit area. However, the result is the opposite with the Huawei Kirin 2026 series chipsets.

On the flip side, LogicFolding maintains the same performance in the Kirin 2026 chip while letting it achieve 29 TPOS of computing power, a voltage reduction of 0.30V, and a 73% reduction in power density. Speaking of the tests, here are the results:

• 61 FPS condition: GPU operates at 200mV lower than the Kirin 9030 Pro, leading to a 58% reduction in power consumption.
• HNX testing: CPU achieved the same performance as the Kirin 9030 Pro but with 18% improvements, 9% lower frequency, 200mV lower voltage, and 41% reduced power consumption.
• Turbo Mode: Kirin 2026 NPU reaches 70 TPOS (maximum), a 141% improvement over its predecessor, and improves GPU frame rate by 42%.

(Image Credits: Huawei)

Further, some measurements showed that the typical core wiring length can go down by 20% after folding, shortening some critical paths in data transmission by up to 70%. The clock wiring of processing modules is reduced by 28%.

He Tingbo said:

“LogicFolding does not inherently mean that stacked chips are more power-efficient. Huawei chose to use the performance and latency margins provided by LogicFolding to reduce voltage and power consumption. If the focus was on pursuing performance, the power density could exceed that of previous versions.”