{"id":7060220,"date":"2026-09-18T15:29:01","date_gmt":"2026-09-18T15:29:01","guid":{"rendered":"https:\/\/peraltafinancing.com\/5g-technology\/basics-of-phase-locked-loops-from-analog-only-to-all-digital-part-1\/"},"modified":"2026-09-18T15:29:01","modified_gmt":"2026-09-18T15:29:01","slug":"basics-of-phase-locked-loops-from-analog-only-to-all-digital-part-1","status":"publish","type":"post","link":"https:\/\/fivemor.com\/?p=7060220","title":{"rendered":"Basics of phase-locked loops, from analog-only to all-digital: part 1"},"content":{"rendered":"


\n<\/p>\n

\n

Each of the three topologies of this versatile system building block has its place in modern systems.<\/em><\/p>\n

The phase-locked loop (PLL) plays a vital role in many electronic systems and circuits. It has been used in various forms since the 1930s, providing diverse functions, all related to timing, clocking, frequency synthesis, synchronization, and signal recovery.<\/p>\n

Note that it is called a phase-locked loop, yet many of the applications are centered on frequency rather than phase \u2014 so perhaps it should be called a frequency-locked loop, but that\u2019s not the case. However, there is a close and intimate relationship between phase and frequency, as frequency is the time derivative of phase, just as acceleration is the time derivative of velocity.<\/p>\n

Bolstering the \u201cphase\u201d nomenclature, from an operational perspective, the PLL really is a phase-driven device. Its operation is driven by a phase difference, while frequency requires looking over a longer time period. Phase is the instantaneous position along the continuum of a periodic signal, while frequency is continuing flow and timing. Thus, the term \u201cphase\u201d is more indicative of its operation.<\/p>\n

This article will briefly review the original all-analog PLL and its successor, the digital PLL with some analog elements (often called a hybrid PLL). Finally, it will then look at the latest implementation for this critical function: the all-digital PLL (ADPLL).<\/p>\n

It will not go into operational details as these are covered in countless articles, books, and more with perspectives ranging from qualitative overviews to intense modeling, analysis, equations, and considerations. It will briefly look at issues associated with the all-analog and hybrid PLLs. As one professor noted many years ago (sorry, I don\u2019t recall the specific citation; I am paraphrasing from memory): \u201cThe PLL is the electric engineer\u2019s equivalent to Shakespeare or James Joyce, as it has been the topic of countless graduate-level papers.\u201d<\/p>\n

For tangible evidence of the PLL\u2019s longevity and importance, the seminal analysis of PLL operation, performance, error sources, and noise issues is the book \u201cPhaselock Techniques<\/a>\u201d by Floyd M. Gardner, first published in 1966 and now in its third edition (2005). It\u2019s unusual to see any academic analysis of PLLs that does not cite this work, even in the 2020s.<\/p>\n

A brief history of PLLs<\/strong><\/h3>\n

The first PLLs were built in the 1930s using vacuum-tube circuitry. Their primary application was to align and synchronize two analog carriers for demodulation of signals (\u201cdigital\u201d data as we know it today did not exist yet). Given the complexities of the arrangement, the PLL was only used in high-end and classified military installations, as well as some long-distance broadcast radio links.<\/p>\n

The development of the solid-state transistor simplified the construction of PLLs while reducing their cost, power needs, and size. Still, it was a special circuit to be used only if there was no alternative. However, there soon was a mass application when consumer analog-based color TV was introduced in the 1950s. Each TV set receiver included a special PLL design to synchronize the received color-subcarrier at 3.58 MHz to the internal crystal in the receiver (this analog TV standard served until it was declared obsolete in 2009).<\/p>\n

\"\"